M48Z129V-70PM1中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

SUMMARY DESCRIPTION

The M48Z129Y/V ZEROPOWER? SRAM is a 1,048,576 bit non-volatile static RAM organized as 131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic 32-pin DIP Module. The

M48Z129Y/V directly replaces industry standard 128K x 8 SRAM. It also provides the non-volatility of FLASH without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.

FEATURES SUMMARY

■ INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY

■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES

■ 10 YEARS OF DATA RETENTION IN THE ABSENCE OF POWER

■ MICROPROCESSOR POWER-ON RESET(RESET VALID EVEN DURING BATTERY BACK-UP MODE)

■ BATTERY LOW PIN - PROVIDES WARNING OF BATTERY END-OF-LIFE

■ AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION

■ WRITE PROTECT VOLTAGES (VPFD= Power-fail Deselect Voltage):

– M48Z129Y: VCC= 4.5 to 5.5V 4.2V ≤VPFD ≤4.5V

– M48Z129V: VCC= 3.0 to 3.6V 2.7V ≤VPFD ≤3.0V

■ SELF-CONTAINED BATTERY IN THE CAPHAT? DIP PACKAGE

■ PIN AND FUNCTION COMPATIBLE WITH JEDEC STANDARD 128K x 8 SRAMs