M48Z35Y-70PC1集成電路（IC）的存儲(chǔ)器規(guī)格書PDF中文資料

M48Z35Y-70PC1屬于集成電路（IC）的存儲(chǔ)器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的M48Z35Y-70PC1存儲(chǔ)器存儲(chǔ)器是集成電路上用作數(shù)據(jù)存儲(chǔ)設(shè)備的半導(dǎo)體器件。這些器件分為非易失性或易失性兩種，格式包括 CBRAM、DRAM、EEPROM、EERAM、EPROM、閃存、FRAM、NVSRAM、PCM (PRAM)、PSRAM、RAM 和 SRAM。這些器件的存儲(chǔ)容量為 64 b 至 6 Tb 不等，接口有 I2C、MMC、并行、eMMC、串行、單線、SPI、UFS、Xccela 總線和 1-線。

Description

The M48Z35/Y ZEROPOWER? RAM is a 32K x 8, non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution.

Features

■ Integrated, ultra low power SRAM, power-fail

control circuit, and battery

■ READ cycle time equals WRITE cycle time

■ Automatic power-fail chip deselect and WRITE

protection

■ WRITE protect voltages:

(VPFD = Power-fail Deselect Voltage)

– M48Z35: VCC = 4.75 to 5.5V

4.5V ≤ VPFD ≤ 4.75V

– M48Z35Y: 4.5 to 5.5V

4.2v ≤ Vpfd ≤ 4.5v

■ Self-contained battery in the CAPHAT? DIP

package

■ Packaging includes a 28-lead SOIC and

SNAPHAT? top (to be ordered separately)

■ Pin and function compatible with JEDEC

standard 32K x 8 SRAMs

■ SOIC package provides direct connection for a

SNAPHAT top which contains the battery

■ RoHS compliant

– Lead-free second level interconnect