M5M4V16169DTP-7中文資料三菱電機數據手冊PDF規(guī)格書

DESCRIPTION

The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word by 16-bit static RAM array as a Cache memory (block size 8x16) onto a single monolithic circuit. The block data transfer between the DRAM and the data transfer buffers (RB1/RB2/WB1/WB2) is performed in one instruction cycle, a fundamental advantage over a conventional DRAM/SRAM cache.

The RAM is fabricated with a high performance CMOS process, and is ideal for large-capacity memory systems where high speed, low power dissipation, and low cost are essential. The use of quadruple-layer polysilicon process combined with silicide and double layer aluminum wiring technology, a single-transistor dynamic storage stacked capacitor cell, and a six-transistor static storage cache cell provide high circuit density at reduced costs.

FEATURES

# 70-pin,400-mil TSOP (type II ) with 0.65mm lead pitch and 23.49mm package length.

# Multiplexed DRAM address inputs for reduced pin count and higher system densities.

# Selectable output operation (transparent / latched / registered) using set command register cycle.

# Single 3.3V +/- 0.3V Power Supply. (3.3V +/- 0.15V for -7 part)

# 2048 refresh cycles every 64ms (Ad0->Ad10).

# Programmable burst length (1,2,4,8) and burst sequence (sequential,interleave) with no latency.

# Synchronous design for precise control with an external clock (K).

# Output retention by advanced mask clock (CMs#).

# All inputs/outputs low capacitance and LVTTL compatible.

# Separate DRAM and SRAM address inputs for fast SRAM access.

# Page Mode capability.

# Auto Refresh capability.

# Self Refresh capability.