M5M4V16G50DFP-10中文資料三菱電機(jī)數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The M5M4V16G50DFP is a 2-bank x 262,144-word x 32-bit Synchronous GRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V16G50DFP can operate at frequencies of 100+ MHz. The BLOCK WRITE and WRITE-PER-BIT functions provide improved performance in graphic memory systems

FEATURES

- Single 3.3v±0.3v power supply

- Clock frequencies of 125 MHz

- Fully synchronous operation referenced to clock rising edge

- Dual bank operation controlled by A10(Bank Address)

- Internal pipelined operation: column address can be changed every clock cycle

- Programmable /CAS Latency (LVTTL: 2 and 3)

- Programmable Burst Length (1/2/4/8 and Full Page)

- Programmable Burst Type (Sequential / Interleave)

- Byte control using DQM0 - DQM3 signals in both read and write cycles

- Persistent Write-Per-Bit (WPB) function

- 8 Column Block Write (BW) function

- Auto Precharge / All bank precharge controlled by A9

- Auto Refresh and Self Refresh Capability

- 2048 refresh cycles /32ms

- LVTTL Interface

- 100 pin QFP package with 0.65mm lead pitch