M5M5V5636GP-16中文資料三菱電機數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The M5M5V5636GP is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishis SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5V5636GP operates on 3.3V power/ 2.5V I/O supply or a single 3.3V power supply and are 3.3V CMOS compatible.

FEATURES

? Fully registered inputs and outputs for pipelined operation

? Fast clock speed: 167 MHz

? Fast access time: 3.8 ns

? Single 3.3V -5 and +5 power supply VDD

? Separate VDDQ for 3.3V or 2.5V I/O

? Individual byte write (BWa# - BWd#) controls may be tied LOW

? Single Read/Write control pin (W#)

? CKE# pin to enable clock and suspend operations

? Internally self-timed, registers outputs eliminate the need to control G#

? Snooze mode (ZZ) for power down

? Linear or Interleaved Burst Modes

? Three chip enables for simple depth expansion

APPLICATION

High-end networking products that require high bandwidth, such as switches and routers.