M66252P中文資料三菱電機數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology.

It has separate clock, enable and reset signals for write and read and is most suitable as a buffer memory between devices with different data processing throughput.

FEATURES

? Memory construction ...................................... 1152words x 8bits (dynamic memory)

? High-speed cycle ............................................ 50ns (min.)

? High-speed access ........................................ 40ns (max.)

? Output hold ....................................................... 5ns (min.)

? Fully independent, asynchronous write and read operations

? Variable-length delay bit

? Output .................................................................... 3-state

APPLICATION

Digital photocopiers, high-speed facsimiles, laser beam printers.