M68AF127BL70N6中文資料意法半導體數據手冊PDF規(guī)格書

SUMMARY DESCRIPTION

The M68AF127B is a 1Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 4.5 to 5.5V supply.

This device has an automatic power-down feature, reducing the power consumption by over 99 when deselected.

The M68AF127B is available in SO32, PDIP32, TSOP32 (8x13.4mm) and TSOP32 (8x20mm) packages.

FEATURES SUMMARY

■ SUPPLY VOLTAGE: 4.5 to 5.5V

■ 128K x 8 bits SRAM with OUTPUT ENABLE

■ EQUAL CYCLE and ACCESS TIMES: 55ns

■ LOW STANDBY CURRENT

■ LOW VCC DATA RETENTION: 2V

■ TRI-STATE COMMON I/O

■ LOW ACTIVE and STANDBY POWER