M68AW512MN55ND6T中文資料意法半導體數據手冊PDF規(guī)格書

SUMMARY DESCRIPTION

The M68AW512M is a 8 Mbit (8,388,608 bit) CMOS SRAM, organized as 524,288 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has an automatic power-down feature, reducing the power consumption by over 99 when deselected.

The M68AW512M is available in TSOP44 Type II packages.

FEATURES SUMMARY

■ SUPPLY VOLTAGE: 2.7 to 3.6V

■ 512K x 16 bits SRAM with OUTPUT ENABLE

■ EQUAL CYCLE and ACCESS TIME: 55ns

■ SINGLE BYTE READ/WRITE

■ LOW STANDBY CURRENT

■ LOW VCC DATA RETENTION: 1.5V

■ TRI-STATE COMMON I/O

■ AUTOMATIC POWER DOWN