首頁(yè)>M68Z512-70NC1T>規(guī)格書(shū)詳情
M68Z512-70NC1T中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
| 廠商型號(hào) |
M68Z512-70NC1T |
| 功能描述 | 4 Mbit 512Kb x8 Low Power SRAM with Output Enable |
| 文件大小 |
92.97 Kbytes |
| 頁(yè)面數(shù)量 |
12 頁(yè) |
| 生產(chǎn)廠商 | STMicroelectronics |
| 企業(yè)簡(jiǎn)稱 |
STMICROELECTRONICS【意法半導(dǎo)體】 |
| 中文名稱 | 意法半導(dǎo)體集團(tuán)官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-1-10 11:18:00 |
M68Z512-70NC1T規(guī)格書(shū)詳情
DESCRIPTION
The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V ±10 supply, and all inputs and outputs are TTL compatible.
FEATURES SUMMARY
■ ULTRA LOW DATA RETENTION CURRENT
– 100nA (typical)
– 10μA (max)
■ OPERATION VOLTAGE: 5.0V ± 10
■ 512 Kbit x 8 SRAM WITH OUTPUT ENABLE
■ EQUAL CYCLE and ACCESS TIMES: 70ns
■ LOW VCC DATA RETENTION: 2.0V
■ TRI-STATE COMMON I/O
■ CMOS FOR OPTIMUM SPEED/POWER
■ AUTOMATIC POWER-DOWN WHEN DESELECTED
■ INTENDED FOR USE WITH ST ZEROPOWER? AND TIMEKEEPER? CONTROLLERS
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
ST/意法 |
23+ |
NA/ |
4419 |
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2978 |
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NEWPARTS |
8000 |
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三菱 |
100 |
原裝現(xiàn)貨,價(jià)格優(yōu)惠 |
詢價(jià) | ||||
CHIPS |
22+ |
BGA |
1196 |
大量現(xiàn)貨庫(kù)存,提供一站式服務(wù)! |
詢價(jià) | ||
ST/意法 |
23+ |
TSOPII-32 |
50000 |
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詢價(jià) | ||
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18+ |
QFP |
85600 |
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詢價(jià) | ||
CHIPS |
24+ |
BGA |
30617 |
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詢價(jià) | ||
ST |
TSOPII-32 |
93480 |
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STMICROELECT |
原廠原裝 |
4793 |
只做全新原裝真實(shí)現(xiàn)貨供應(yīng) |
詢價(jià) |
