M74HC165B1R集成電路（IC）的移位寄存器規(guī)格書PDF中文資料

M74HC165B1R屬于集成電路（IC）的移位寄存器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的M74HC165B1R移位寄存器移位寄存器是低級(jí)邏輯器件，通常用于在串行和并行方式之間轉(zhuǎn)換數(shù)字邏輯信號(hào)形式的數(shù)據(jù)，或在數(shù)字字內(nèi)移動(dòng)數(shù)據(jù)位的位置。移位寄存器通常使用集成到一個(gè)設(shè)備中的一組觸發(fā)器來實(shí)現(xiàn)，常用于集成度更高的邏輯器件，但仍可用于 I/O 擴(kuò)展等應(yīng)用，在這些應(yīng)用中離散形式的函數(shù)可能會(huì)非常有用。

Description

The M74HC165 is a high speed CMOS 8-bit PISO (parallel-in-serial-out) shift register fabricated with silicon gate C2MOS technology. This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. The parallel data enter when the shift/load input is low and can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock inputs perform identically: one can be used as a clock inhibit by applying a high signal, to allow this operation clocking is accomplished through a 2-input nor gate. To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal causes the same response as rising clock edge. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

Features

■ High speed:

– tPD = 15 ns (typ.) at VCC = 6 V

■ Low power dissipation:

– ICC = 4 μA (max.) at TA = 25 °C

■ High noise immunity:

VNIH = VNIL = 28 VCC (Min.)

■ Symmetrical output impedance:

|IOH| = IOL = 4 mA (min)

■ Balanced propagation delays: tPLH ? tPHL

■ Wide operating voltage range:

VCC (opr) = 2 V to 6 V

■ Pin and function compatible with 74 series 165