DESCRIPTION

The M54/74HCT540 and HCT541 are high speed CMOS OCTAL BUS BUFFERS (3-STATE) fabricated in silicon gate C2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. The HCT540 is an inverting buffer and HCT541 is a non inverting buffer.

The 3 STATE control gate operates as a two input AND such that if either G1 and G2 are high, all eight outputs are in the high impedance state. In order to enhance PC board layout, the HCT540 and HCT541 offers a pinout having inputs and outputs on opposite sides of the package. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

This integrated circuit has input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption.

■ HIGH SPEED tPD = 10 ns (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION ICC = 4 μA (MAX.) at TA = 25 °C

■ COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX.)

■ OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS

■ SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 6 mA (MIN)

■ BALANCED PROPAGATION DELAYS tPLH = tPHL

■ PIN AND FUNCTION COMPATIBLE WITH 54/74LS540/541

M74HCT541屬于集成電路（IC） > 緩沖器，驅動器，接收器，收發(fā)器。意法半導體（ST）集團制造生產的M74HCT541緩沖器，驅動器，接收器，收發(fā)器邏輯緩沖器、驅動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅動負載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數據總線之間進行隔離通信。