MAX3674集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

General Description

The MAX3674 is a high-performance network clock synthesizer IC for networking, computing, and telecom applications. It integrates a crystal oscillator, a lownoise phase-locked loop (PLL), programmable dividers, and high-frequency LVPECL output buffers. The PLL generates a high-frequency clock based on a low-frequency reference clock provided by the on-chip crystal oscillator or an external LVCMOS clock. The MAX3674 has excellent period jitter, cycle-to-cycle jitter, and supply noise rejection performance. With output frequencies programmable from 21.25MHz to 1360MHz and support of two differential PECL output signals, the device provides a versatile solution for the most demanding clock applications.

Features

? 21.25MHz to 1360MHz Programmable PLL Synthesized Output Clocks

? Two Differential LVPECL-Compatible Outputs

? Cycle-to-Cycle Jitter 1.6ps RMS and Period Jitter 0.9ps RMS at 500MHz

? On-Chip Crystal Oscillator or Selectable LVCMOS-Compatible Reference Clock Input

? Excellent Power-Supply Noise Rejection

? Parallel or 2-Wire I2C Programming Interface

? Lock Indicator Output

? +3.3V Power Supply

? Power Consumption: 396mW at 3.3V

? 48-Pin LQFP Pb-Free Package

? -40°C to +85°C Temperature Range

Applications

??? Ethernet Network ASIC Clock Generation

??? Storage Area Network ASIC Clocking

??? Optical Network ASIC Clocking

??? Programmable Clock Source for Server, Computing, or Communication Systems

??? Frequency Margining