MAX9424EGJ中文資料美信數(shù)據(jù)手冊PDF規(guī)格書

General Description

The MAX9424–MAX9427 high-speed, low-skew quad PECL-to-ECL translators are designed for high-speed data and clock driver applications. These devices feature an ultra-low 0.24ps(RMS) random jitter and channel-to channel skew is less than 90ps in asynchronous mode.

The four channels can be operated synchronously with an external clock, or in asynchronous mode determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state.

Features

? 0.24ps RMS Added Random Jitter

? 10ps Channel-to-Channel Skew in Synchronous Mode

? Guaranteed 500mV Differential Output at 3GHz Clock Frequency

? 420ps Propagation Delay in Asynchronous Mode

? Functionally Compatible with

?? SK4426 (MAX9424)

?? SK4430 (MAX9425)

?? SK4436 (MAX9426)

?? SK4440 (MAX9427)

? Integrated 50? Outputs (MAX9425/MAX9427)

? Integrated 100? Inputs (MAX9426/MAX9427)

? Synchronous/Asynchronous Operation

Applications

? Data and Clock Driver and Buffer

? Central Office Backplane Clock Distribution

? DSLAM Backplane

? Base Station

? ATE

?