MB81416-15中文資料富士通數(shù)據(jù)手冊PDF規(guī)格書

Description

The Fujitsu MB81416 is a fully decoded, dynamic NMOS random access memory organized as 16384 words by 4-bits. The design is optimized for high speed, high performance applications such as mainframe memory, buffer memory, peripheral storage and en- vironments where low power dissipation and compact layout are required. Multiplexed row and column address Inputs permit the MB81416 to be housed in a standard 18-pin DIP that is compatible with the JEDEC approved pinout. Greater refresh versatility is provided by a new CAS before RAS on-chip refresh capability. The MB81416 also features page mode which allows high speed random ac- cess of up to 64 nibble wide words within the same row address. The MB81416 is fabricated using silicon gate NMOS and Fujitsu's advanced Double-Layer Polysilicon process. This process, coupled with single-transistor memory storage cells, permits maximum cir- cuit density and minimal chip size. Dynamic circuitry is employed in the design, including the sense amplifiers. Clock timing requirements are non-critical, and the power supply tolerance is very wide. All inputs and outputs are TTL compatible.

Features

Organized as 16384 words by 4-bits Row Access Time/Cycle Time: MB81416-10 100nsec max/200 min. MB81416-12 120nsec max/230 min. MB81416-15 150nsec max/260 min. I Low Active Power (tac min) MB81416-10 303mW (max.) MB81416-12 275mW (max.) MB81416-15 248mW (max.) All devices 25mW standby Single +5V ±10 Power Supply CAS before RAS Refresh RAS Only Refresh Hidden CAS before RAS Refresh I 2ms/128 cycle Refresh (A-Ag) Read-Modify-Write Capability Page Mode Capability for faster access Output unlatched at cycle end Early Write or Output Enable controls output buffer Im pedance On Chip Address and Data-in latches Standard 18-pin DIP All Inputs TTL Compatible, low capacitive load Three-State TTL Compatible Outputs On-chip Substrate Bias Generator