MB84VB2001-10中文資料富士通數(shù)據(jù)手冊PDF規(guī)格書

■ FEATURES

? Contain 2 chips of MBM29LV800A, and each chip have separate CE.

? Power supply voltage of 2.7 to 3.6 V

? High performance

100 ns maximum access time

? Operating Temperature

–40 to +85°C

? Minimum 100,000 write/erase cycles

? Sector erase architecture

One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes × 2 chips

Any combination of sectors can be concurrently erased. Also supports full chip erase.

? Boot Code Sector Architecture

MB84VB2000: Top sector

MB84VB2001: Bottom sector

? Embedded EraseTM Algorithms

Automatically pre-programs and erases the chip or any sector

? Embedded ProgramTM Algorithms

Automatically writes and verifies data at specified address

? Data Polling and Toggle Bit feature for detection of program or erase cycle completion

? Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

? Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

? Low VCC write inhibit ≤ 2.5 V

? Erase Suspend/Resume

Suspends the erase operation to allow a read data in another sector within the same device

? Please refer to MBM29LV800TA/BA data sheet in detailed function