MB89P558A中文資料富士通數(shù)據(jù)手冊PDF規(guī)格書

■ DESCRIPTION

The MB89550A series is a general-purpose, single-chip microcontroller that features a compact instruction set and contains a range of peripheral functions including a dual- clock control system, 5-level operating speed control, LCD controller driver, A/D converter, D/A converter, timer, serial interface, PWM timer, PWC timer, and external interrupts. The LCD controller driver is particularly suited for simultaneous control of LCD duty drive and static drive functions.

■ FEATURES

? Range of package options

? LQFP package (0.5 mm pitch)

? TQFP package (0.4 mm pitch)

? High speed operation at low voltage

? Minimum instruction execution time 0.32 μs (for 12.5 MHz oscillation)

? F2MCR-8L CPU core

Instruction set optimized for controller applications

? Multiplication and division instructions

? 16-bit arithmetic operations

? Bit test branch instructions

? Bit manipulation instructions, etc.

? Dual-clock control system

? Main clock 12.5 MHz maximum : (Four speed settings available, oscillation halts in sub-clock mode)

? Sub-clock 32.768 kHz : (Operation clock for sub-clock mode)

? 11 timer systems

? 8/16-bit timer counter 1 (square wave output, 2-channel output switching available)

? 8/16-bit timer counter 2 (square wave output, 2-channel output switching available)

? 16-bit timer counter (also functions as event counter)

? 8-bit PWM timer (8-bit PWM timer × 2 channels or PPG timer × 1 channel, includes event counter function)

? 8-bit PWC timer (8-bit PWC timer × 1 channel)

? 6-bit PPG timer (6-bit PPG timer × 1 channel)

? 21-bit timebase timer

? Clock prescaler (17-bit)

? UART/serial interface

? UART/SIO switching

? UART

? Clock synchronous/asynchronous switching available

? 10-bit A/D converter

? 10-bit A/D × 8 channels

? 8-bit D/A converter

? 8-bit D/A × 2 channels

? External interrupts

? Eight independent inputs can be used for recovery from low-power consumption modes (selection of rising, falling, or both edge detection functions).

? Eight independent inputs can be used for recovery from low-power consumption modes (L level detection function included).

? Clock output functions

? High speed clock signal multiplied by 2 available as output from HCLK pin.

? Low speed clock pulse output available from LCLK pin.

? LCD controller driver

? 32SEG × 4COM (maximum 128 pixels)

8 dedicated to segment output only

8 for port or segment use

16 for port, segment, or static use

? Built-in step-up power supply for driving LCD (optionally available)

? Low-power consumption modes (standby modes)

? Stop mode (all oscillations halt in sub-clock mode, current consumption falls to almost zero)

? Sleep mode (the CPU stops to reduce current consumption to approximately 1/3 of normal)

? Clock mode (all operations other than the clock prescaler halt, current consumption is very low)

? Sub clock mode (systems operate on sub-clock signals)

? Maximum 66 I/O ports

? General-purpose I/O ports (N-ch open drain) : 4

? General-purpose I/O ports (N-ch open drain) : 24

? [also function as LCD ports, with restrictions]

? General purpose I/O ports (CMOS) : 38