MB90652A中文資料富士通數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

■ DESCRIPTION

The MB90650A series are 16-bit microcontrollers designed for high speed real-time processing in consumer product applications such as controlling celluar phones, CD-ROMs, or VTRs. Based on the F2MC*1-16L CPU core, an F2MC-16L is used as the CPU. This CPU includes high-level language-support instructions and robust task switching instructions, and additional addressing modes. In order to reduce the consumption current, dual clock (main/sub) is used. Furthermore, low consumption power supply is achieved by using stop mode, sleep mode, watch mode, pseudo-watch mode, CPU intermittent operation mode. Microcontrollers in this series have built-in peripheral resources including 10-bit A/D converter, 8-bit D/A converter, UART, 8/16-bit PPG, 8/16-bit up/down counter/timer, I2C interface*2, 8/16-bit I/O timer (input capture, output compare, and 16-bit free-run timer).

*1:F2MC stands for FUJITSU Flexible Microcontroller.

*2:Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined

by Philips.

■ FEATURES

F2MC-16L CPU

? Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4

? Instruction set optimized for controller applications

Object code compatibility with F2MC-16(H)

Wide range of data types (bit, byte, word, and long word)

Improved instruction cycles provide increased speed

Additional addressing modes: 23 modes

High code efficiency

Access methods (bank access, linear pointer)

High precision operations are enhanced by use of a 32-bit accumulator

Extended intelligent I/O service (access area extended to 64 Kbytes)

Maximum memory space: 16 Mbytes

? Enhanced high level language (C) and multitasking support instructions

Use of a system stack pointer

Enhanced pointer indirect instructions

Barrel shift instructions

? Improved execution speed: Four byte instruction queue

? Powerful interrupt function

? Automatic data transfer function that does not use instruction (extended I2OS)