■ DESCRIPTION

The MB90480/485 series is a 16-bit general-purpose FUJITSU microcontroller designed for process control in consumer devices and other applications requiring high-speed real-time processing.

The F2MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing.

■ FEATURES

? Clock

Minimum instruction execution time:

40.0 ns/6.25 MHz base frequency multiplied ×4 (25 MHz internal operating

frequency/3.3 V ± 0.3 V)

62.5 ns/4 MHz base frequency multiplied × 4 (16 MHz internal operating

frequency/3.0 V ± 0.3 V) PLL clock multiplier

? Maximum memory space: 16 Mbyte

? Instruction set optimized for controller applications

Supported data types (bit, byte, word, or long word)

Typical addressing modes (23 types)

Enhanced signed multiplication/division instruction and RETI instruction functions

32-bit accumulator for enhanced high-precision calculation

? Instruction set designed for high-level language (C) and multi-task operations

System stack pointer adopted

Instruction set compatibility and barrel shift instructions

? Non-multiplex bus/multiplex bus compatible

? Enhanced execution speed

4 byte instruction queue

? Enhanced interrupt functions

8 levels setting with programmable priority, 8 external interrupts

? Data transmission function (μDMA)

Up to 16 channels

? Embedded ROM

Flash versions : 192 KB, 256 KB, MASK versions : 192 KB

? Embedded RAM

Flash versions : 4 KB, 6 KB, 10 KB, MASK versions : 10 KB

? General purpose ports

Up to 84 ports

(Except MB90V480 : Includes 16 ports with input pull-up resistance, 16 ports with output open drain settings)

? A/D converter

8-channel RC sequential comparison type (10-bit resolution, 3.68 μs conversion time (at 25 MHz) )

? I2C interface (MB90485 series only) :

1channel, P76/P77 Nch OD pin (without Pch)

Do not apply high voltage in excess of recommended operating ranges

to the Nch open drain pin (with Pch) in MB90V485.

? μPG (MB90485 series only) : 1 channel

? UART: 1 channel

? I/O expanded serial interface (SIO) : 2 channels

? 8/16-bit PPG: 3 channels (with 8-bit × 6 channel/16-bit × 3 channel mode switching function)

? 8/16-bit up/down timer: 1 channel (with 8-bit × 2 channel/16-bit × 1-channel mode switching function)

? PWC (MB90485 series only) : 3 channels (Capable of compare the inputs to two of the three)

? 3 V/5 V I/F pin (MB90485 series only)

P20 to P27, P30 to P37, P40 to P47, P70 to P77

? 16-bit reload timer: 1 channel

? 16-bit I/O timer: 2-channel input capture, 6-channel output compare, 1-channel free run timer

? On chip dual clock generator system

? Low-power consumption mode

With stop mode, sleep mode, CPU intermittent operation mode, watch mode, timebase timer mode

? Packages: QFP 100/LQFP 100

? Process: CMOS technology

? Power supply voltage: 3 V, single source (some ports can be operated by 5 V power supply at MB90485 series)