MB91121PFV中文資料富士通數(shù)據(jù)手冊PDF規(guī)格書

■ DESCRIPTION

The MB91121 is a microcontroller with a 32-bit RISC CPU (FR family *) as the core, incorporating a variety of I/O resources, a bus control facility, and a multiplier-accumulator (simplified DSP) with internal program RAM for built-in control applications which require advanced, high-speed CPU processing.

■ FEATURES

1. FR CPU

? 32-bit RISC, load/store architecture, 5-stage pipeline

? Operating clock frequency : Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)

? General purpose registers : 32 bits × 16

? 16-bit fixed length instructions (basic instructions) , 1 instruction/1 cycle

? Memory to memory transfer, bit processing, barrel shifter processing : Optimized for embedded applications

? Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages

? Register interlock functions, efficient assembly language coding

? Branch instructions with delay slots : Reduced overhead time in branch executions

? Internal multiplier/supported at instruction level

Signed 32-bit multiplication : 5 cycles

Signed 16-bit multiplication : 3 cycles

? Interrupt (push PC and PS) : 6 cycles, 16 priority levels

2. Bus interface

? Clock doubler : Internal 50 MHz, external bus 25 MHz operation

? 25-bit address bus (32 Mbytes memory space)

? 8/16-bit data bus

? Basic external bus cycle : 2 clock cycles

? Chip select outputs for setting down to a minimum memory block size of 64 Kbytes : 6

? Interface supported for various memory technologies DRAM interface (area 4 and 5)

? Automatic wait cycle insertion : Flexible setting, from 0 to 7 for each area

? Unused data/address pins can be configured as input/output ports.

? Little endian mode supported (Select 1 area from area 1 to 5)

3. DRAM interface

? 2 banks independent control (area 4 and 5)

? Double CAS DRAM (Normal DRAM I/F) /Single CAS DRAM/Hyper DRAM

? Basic bus cycle : Normally 5 cycles, 2-cycle access possible in high-speed page mode

? Programmable waveform : Automatic 1-cycle wait insertion to RAS and CAS cycles

? DRAM refresh

CBR refresh (interval time configurable by 6-bit timer)

Self-refresh mode

? Supports 8/9/10/12-bit column address width

? 2CAS/1WE, 2WE/1CAS selective

? Lock feature: Keeping a specific program code resident in the cache

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