MC100E195集成電路（IC）的延遲線規(guī)格書PDF中文資料

MC100E195屬于集成電路（IC）的延遲線。由安森美半導(dǎo)體公司制造生產(chǎn)的MC100E195延遲線時鐘延遲線產(chǎn)品族中的產(chǎn)品屬于數(shù)字器件，用于在數(shù)字信號中引入時間延遲，以便將提交給器件輸入的信號躍遷，經(jīng)過某一已知時間之后在輸出端復(fù)現(xiàn)。它們常用于高速數(shù)字系統(tǒng)，以校正或補(bǔ)償不同信號路徑之間的信號傳播時間的偏差。這些器件可用于產(chǎn)生固定、可選或可變持續(xù)時間的延遲。

Description

The MC10E/100E195 is a programmable delay chip (PDC) designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.

The delay section consists of a chain of gates organized as shown in the logic symbol. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps. These two elements provide the E195 with a digitally-selectable resolution of approximately 20 ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on chip by a high signal on the latch enable (LEN) control.

Because the delay programmability of the E195 is achieved by purely differential ECL gate delays the device will operate at frequencies of > 1.0 GHz while maintaining over 600 mV of output swing.

The E195 thus offers very fine resolution, at very high frequencies, that is selectable entirely from a digital input allowing for very accurate system clock timing.

An eighth latched input, D7, is provided for cascading multiple PDC’s for increased programmable range. The cascade logic allows full control of multiple PDC’s, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating.

The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 μF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.

Features

? 2.0 ns Worst Case Delay Range

? ≈ 20 ps/Delay Step Resolution

? > 1.0 GHz Bandwidth

? On Chip Cascade Circuitry

? PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V

? NECL Mode Operating Range: VCC = 0 V with VEE = ?4.2 V to ?5.7 V

? Internal Input 50 kΩ Pulldown Resistors

? ESD Protection:

? > 2 kV Human Body Model

? > 200 V Machine Model

? Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

? Moisture Sensitivity: Level 3 (Pb-Free)

(For Additional Information, see Application Note AND8003/D)

? Flammability Rating: UL 94 V?0 @ 0.125 in Oxygen Index: 28 to 34

? Transistor Count = 368 Devices

? These Devices are Pb-Free, Halogen Free and are RoHS Compliant