MC100E336中文資料安森美半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書
MC100E336規(guī)格書詳情
The MC10E/MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs (BUS0–BUS2) are specified for driving a 25 ? bus; the receive outputs (Q0 – Q2) are specified for 50 ?. The bus outputs feature a normal HIGH level (VOH) and a cutoff LOW level — when LOW, the outputs go to –2.0 V and the output emitter-follower is “off”, presenting a high impedance to the bus. The bus outputs also feature edge slow-down capacitors.
The 100 Series contains temperature compensation.
? 25 ? Cutoff Bus Outputs
? 50 ? Receiver Outputs
? Transmit and Receive Registers
? 1500 ps Max. Clock to Bus
? 1000 ps Max. Clock to Q
? Bus Outputs Feature Internal Edge Slow-Down Capacitors
? Additional Package Ground Pins
? PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V
? NECL Mode Operating Range: VCC= 0 V with VEE= –4.2 V to –5.7 V
? Internal Input Pulldown Resistors
? ESD Protection: > 1 KV HBM, > 75 V MM
? Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
? Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D
? Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34
? Transistor Count = 430 devices
產(chǎn)品屬性
- 型號(hào):
MC100E336
- 制造商:
ONSEMI
- 制造商全稱:
ON Semiconductor
- 功能描述:
3-BIT REGISTERED BUS TRANSCEIVER
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
ON |
03+ |
PLCC28 |
777 |
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23+ |
6000 |
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23+ |
PLCC |
9526 |
詢價(jià) | |||
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23+ |
SMD |
1407 |
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24+ |
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2250 |
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ON |
24+ |
PLCC-28 |
6980 |
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詢價(jià) | ||
M0T |
PLCC28 |
68900 |
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詢價(jià) | |||
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13000 |
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9146 |
29 |
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23+ |
NA/ |
10545 |
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詢價(jià) |