The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition.

The 100 Series contains temperature compensation.

? Maximum Input Clock Frequency >1.2 GHz Typical

? Programmable Range: 0 ns to 10 ns

? Delay Range: 2.2 ns to 12.2 ns

? 10 ps Increments

? PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V

? NECL Mode Operating Range: VCC = 0 V with VEE = ?3.0 V to ?3.6 V

? Open Input Default State

? Safety Clamp on Inputs

? A Logic High on the EN Pin Will Force Q to Logic Low

? D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL Inputs

? VBB Output Reference Voltage

? Pb?Free Packages are Available

MC100EP195FA屬于集成電路（IC） > 延遲線。安森美半導(dǎo)體公司制造生產(chǎn)的MC100EP195FA延遲線時(shí)鐘延遲線產(chǎn)品族中的產(chǎn)品屬于數(shù)字器件，用于在數(shù)字信號(hào)中引入時(shí)間延遲，以便將提交給器件輸入的信號(hào)躍遷，經(jīng)過(guò)某一已知時(shí)間之后在輸出端復(fù)現(xiàn)。它們常用于高速數(shù)字系統(tǒng)，以校正或補(bǔ)償不同信號(hào)路徑之間的信號(hào)傳播時(shí)間的偏差。這些器件可用于產(chǎn)生固定、可選或可變持續(xù)時(shí)間的延遲。