Description

The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single?ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

Features

? 50 ps Typical Output-to-Output Skew

? Synchronous Enable/Disable

? Master Reset for Synchronization

? 1.5 GHz Toggle Frequency

? The 100 Series Contains Temperature Compensation.

? PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V

? NECL Mode Operating Range: VCC = 0 V with VEE = ?3.0 V to ?3.8 V

? Open Input Default State

? LVDS Input Compatible

? Pb?Free Packages are Available

MC100LVEL34DT屬于集成電路（IC） > 時鐘發(fā)生器，PLL，頻率合成器。安森美半導體公司制造生產(chǎn)的MC100LVEL34DT時鐘發(fā)生器，PLL，頻率合成器時鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號的穩(wěn)定定時脈沖，這些器件包括計算機、微控制器、數(shù)據(jù)通信系統(tǒng)和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅(qū)動器、分頻器、倍頻器、多路復用器、合成器、扇出分配器和預分頻器。