MC10E256中文資料安森美半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
廠商型號(hào) |
MC10E256 |
功能描述 | 3-BIT 4:1 MUX-LATCH |
文件大小 |
110.02 Kbytes |
頁(yè)面數(shù)量 |
5 頁(yè) |
生產(chǎn)廠商 | ON Semiconductor |
企業(yè)簡(jiǎn)稱(chēng) |
ONSEMI【安森美半導(dǎo)體】 |
中文名稱(chēng) | 安森美半導(dǎo)體公司官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2024-11-2 11:15:00 |
MC10E256規(guī)格書(shū)詳情
The MC10E/100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs (see logic symbol).
When the Latch Enable (LEN) is LOW, the latch is transparent, and output data is controlled by the multiplexer select controls. A logic HIGH on LEN latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.
The 100 Series contains temperature compensation
? 950 ps Max. D to Output
? 850 ps Max. LEN to Output
? Split Select
? Differential Outputs
? PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V
? NECL Mode Operating Range: VCC= 0 V with VEE= –4.2 V to –5.7 V
? Internal Input Pulldown Resistors
? ESD Protection: > 1 KV HBM, > 75 V MM
? Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
? Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D
? Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34
? Transistor Count = 280 devices
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---|---|---|---|---|---|---|---|
ONsemi |
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詢(xún)價(jià) | ||
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詢(xún)價(jià) | ||
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詢(xún)價(jià) | |||
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詢(xún)價(jià) | ||
ONN |
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636 |
詢(xún)價(jià) |