MC14018BCP集成電路（IC）的計(jì)數(shù)器除法器規(guī)格書PDF中文資料

The MC14018B contains five Johnson counter stages which are asynchronously presettable and resettable. The counters are synchronous, and increment on the positive going edge of the clock. Presetting is accomplished by a logic 1 on the preset enable input. Data on the Jam inputs will then be transferred to their respective Q outputs (inverted). A logic 1 on the reset input will cause all Q outputs to go to a logic 1 state.

Division by any number from 2 to 10 can be accomplished by connecting appropriate Q outputs to the data input, as shown in the Function Selection table. Anti–lock gating is included in the MC14018B to assure proper counting sequence.

? Fully Static Operation

? Schmitt Trigger on Clock Input

? Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range Pin–for–Pin Replacement for CD4018B