首頁>MC14042BFR2>規(guī)格書詳情
MC14042BFR2中文資料安森美半導體數據手冊PDF規(guī)格書
MC14042BFR2規(guī)格書詳情
The MC14042B Quad Transparent Latch is constructed with MOS P?channel and N?channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q during the clock level which is determined by the polarity input. When the polarity input is in the logic “0” state, data is transferred during the low clock level, and when the polarity input is in the logic “1” state the transfer occurs during the high clock level.
Features
? Buffered Data Inputs
? Common Clock
? Clock Polarity Control
? Q and Q Outputs
? Double Diode Input Protection
? Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
? Capable of Driving Two Low?power TTL Loads or One Low?power
Schottky TTL Load Over the Rated Temperature Range
? Pb?Free Packages are Available*
供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
MOTOROLA/摩托羅拉 |
23+ |
DIP |
90000 |
只做自庫存深圳可交貨 |
詢價 | ||
MC14043BCL |
5 |
5 |
詢價 | ||||
ON |
DIP |
90 |
正品原裝--自家現貨-實單可談 |
詢價 | |||
MOT |
2022 |
DIP16 |
3268 |
原廠原裝正品,價格超越代理 |
詢價 | ||
ON |
1822+ |
DIP |
9852 |
只做原裝正品假一賠十為客戶做到零風險!! |
詢價 | ||
ON |
17+ |
DIP |
6200 |
100%原裝正品現貨 |
詢價 | ||
ON |
23+ |
SOP/DIP |
5000 |
原裝正品,假一罰十 |
詢價 | ||
ON/安森美 |
23+ |
DIP |
13000 |
原廠授權一級代理,專業(yè)海外優(yōu)勢訂貨,價格優(yōu)勢、品種 |
詢價 | ||
ON |
24+ |
SOP16 |
90000 |
一級代理商進口原裝現貨、假一罰十價格合理 |
詢價 | ||
24+ |
DIP |
7 |
詢價 |