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MC14049UB_V01中文資料安森美半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

MC14049UB_V01
廠商型號

MC14049UB_V01

功能描述

Hex Buffers

文件大小

201.15 Kbytes

頁面數(shù)量

7

生產(chǎn)廠商 ON Semiconductor
企業(yè)簡稱

ONSEMI安森美半導(dǎo)體

中文名稱

安森美半導(dǎo)體公司官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-3-11 9:38:00

人工找貨

MC14049UB_V01價格和庫存,歡迎聯(lián)系客服免費人工找貨

MC14049UB_V01規(guī)格書詳情

The MC14049UB hex inverter/buffer is constructed with MOS

P?channel and N?channel enhancement mode devices in a single

monolithic structure. This complementary MOS device finds primary

use where low power dissipation and/or high noise immunity is

desired. This device provides logic?level conversion using only one

supply voltage, VDD. The input?signal high level (VIH) can exceed the

VDD supply voltage for logic?level conversions. Two TTL/DTL

Loads can be driven when the device is used as CMOS?to?TTL/DTL

converters (VDD = 5.0 V, VOL ≤ 0.4 V, IOL ≥ 3.2 mA). Note that pins

13 and 16 are not connected internally on this device; consequently

connections to these terminals will not affect circuit operation.

Features

? High Source and Sink Currents

? High?to?Low Level Converter

? Supply Voltage Range = 3.0 V to 18 V

? Meets JEDEC UB Specifications

? VIN can exceed VDD

? Improved ESD Protection on All Inputs

? These Devices are Pb?Free and are RoHS Compliant

? NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC?Q100

Qualified and PPAP Capable

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