The MC14076B 4?Bit Register consists of four D?type flip?flops operating synchronously from a common clock. OR gated output?disable inputs force the outputs into a high?impedance state for use in bus organized systems. OR gated data?disable inputs cause the Q outputs to be fed back to the D inputs of the flip?flops. Thus they are inhibited from changing state while the clocking process remains undisturbed. An asynchronous master root is provided to clear all four flip?flops simultaneously independent of the clock or disable inputs.

Features

? Three?State Outputs with Gated Control Lines

? Fully Independent Clock Allows Unrestricted Operation for the Two

Modes: Parallel Load and Do Nothing

? Asynchronous Master Reset

? Four Bus Buffer Registers

? Supply Voltage Range = 3.0 Vdc to 18 Vdc

? Capable of Driving Two Low?Power TTL Loads or One Low?Power

Schottky TTL Load Over the Rated Temperature Range

? Pb?Free Packages are Available*

MC14076B屬于集成電路（IC） > 觸發(fā)器。安森美半導(dǎo)體公司制造生產(chǎn)的MC14076B觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對(duì)提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。