MC14522BCL中文資料摩托羅拉數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Presettable 4-Bit Down Counters

TheMC14522B BCD counter and the MC14526Bbinary counter are constructed with MOS P–channelandN–channel enhancement mode devices in a monolithic structure. Thesedevices are presettable, cascadable, synchronous down counters with a decoded“0” state output for divide–by–N applications. In single stage applicationsthe “0” output is applied to the Preset Enable input. The CascadeFeedback input allows cascade divide–by–N operation with no additionalgates required. The Inhibit inputallows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock.

Thesecomplementary MOS counters can be used in frequency synthesizers,phase–locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.

? Supply Voltage Range = 3.0 Vdc to 18 Vdc

? Logic Edge–Clocked Design — Incremented on Positive Transition of Clock or Negative Transition of Inhibit

? Asynchronous Preset Enable

? Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range