MC14568B中文資料摩托羅拉數(shù)據(jù)手冊PDF規(guī)格書

The MC14568B consists of a phase comparator, a divide–by–4, 16, 64 or 100 counter and a programmable divide–by–N 4–bit binary counter (all positive–edge triggered) constructed with MOS P–channelandN–channel enhancement mode devices (complementary MOS) in a monolithic structure. TheMC14568B has been designed for use in conjunction with a programmable divide–by–N counter for frequency synthesizers and phase–lockedloop applicationsrequiring low power dissipation and/or high noiseimmunity.

This device can be used with both counters cascaded and the output of thesecond counter connected to the phase comparator (CTL high), or used independentlyof the programmable divide–by–N counter, for example cascaded with a MC14569B, MC14522B or MC14526B (CTL low).

? Supply Voltage Range = 3.0 to 18 V

? Capable of Driving Two Low–Power TTL Loads, One Low–Power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range.

? Chip Complexity: 549 FETs or 137 Equivalent Gates