MC68340CFE8V中文資料飛思卡爾數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

The MC68340 is a high-performance 32-bit integrated processor with direct memory access (DMA), combining an enhanced M68000-compatible processor, 32-bit DMA, and other peripheral subsystems on a single integrated circuit. The MC68340 CPU32 delivers 32-bit CISC processor performance from a lower cost 16-bit memory system. The combination of peripherals offered in the MC68340 can be found in a diverse range of microprocessor-based systems, including embedded control and general computing. Systems requiring very high-speed block transfers of data can especially benefit from the MC68340s DMA.

The primary features of the MC68340 are as follows:

? High Functional Integration on a Single Piece of Silicon

? CPU32—MC68020-Derived 32-Bit Central Processor Unit

— Upward Object-Code Compatible with MC68000 and MC68010

— Additional 32-Bit MC68020 Instructions and Addressing Modes

— Unique Embedded Control Instructions

— Fast Two-Clock Register Instructions—10,045 Dhrystones/Second

? Two-Channel Low-Latency DMA Controller for High-Speed Memory Transfers

— Single- or Dual-Address Transfers

— 32-Bit Addresses and Counters

— 8-, 16-, and 32-Bit Data Transfers

— 50 Mbyte/Sec Sustained Transfers (12.5 Mbyte/Sec Memory-to-Memory)

? Two-Channel Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

— Baud Rate Generators

— Modem Control

— MC68681/MC2681 Compatible

— 9.8 Mbits/Sec Maximum Transfer Rate

? Two Independent Counter/Timers

— 16-Bit Counter

— Up to 8-Bit Prescaler

— Multimode Operation

— 80-ns Resolution

? System Integration Module Incorporates Many Functions Typically Relegated to External PALs, TTL, and ASIC, such as:

— System Configuration — External Bus Interface

— System Protection — Periodic Interrupt Timer

— Chip Select and Wait State Generation — Interrupt Response

— Clock Generation — Bus Arbitration

— Dynamic Bus Sizing — IEEE 1149.1 Boundary Scan (JTAG)

— Up to 16 Discrete I/O Lines — Power-On Reset

? 32 Address Lines, 16 Data Lines

? Power Consumption Control

— Static HCMOS Technology Reduces Power in Normal Operation

— Low Voltage Operation at 3.3 V ±0.3 V (MC68340V only)

— Programmable Clock Generator Throttles Frequency

— Unused Peripherals Can Be Turned Off

— LPSTOP Provides an Idle State for Lowest Standby Current

? 0–16.78 MHz or 0–25.16 MHz Operation

? 144-Pin Ceramic Quad Flat Pack (CQFP) or 145-Pin Plastic Pin Grid Array (PGA)