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MC68HC08AS20中文資料恩智浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書
廠商型號(hào) |
MC68HC08AS20 |
功能描述 | High-Performance M68HC08 Architecture |
文件大小 |
5.20044 Mbytes |
頁面數(shù)量 |
386 頁 |
生產(chǎn)廠商 | NXP Semiconductors |
企業(yè)簡稱 |
nxp【恩智浦】 |
中文名稱 | 恩智浦半導(dǎo)體公司官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2024-11-18 18:30:00 |
MC68HC08AS20規(guī)格書詳情
Features of the MC68HC08AS20 include:
? High-Performance M68HC08 Architecture
? Fully Upward-Compatible Object Code with M6805, M146805,
and M68HC05 Families
? 8.4-MHz Internal Bus Frequency
? 20,480 Bytes of Read-Only Memory (ROM)
? ROM Data Security
? 512 Bytes of On-Chip Electrically Erasable Programmable
Read-Only Memory (EEPROM)
? 640 Bytes of On-Chip RAM
? Serial Peripheral Interface Module (SPI)
? Serial Communications Interface Module (SCI)
? 16-Bit, 6-Channel Timer Interface Module (TIM)
? Clock Generator Module (CGM)
? 8-Bit, 15-Channel Analog-to-Digital Converter Module (ADC)
? SAE J1850 Byte Data Link Controller Digital Module (BDLC–D)
? System Protection Features
– Computer Operating Properly (COP) with Optional Reset
– Low-Voltage Detection with Optional Reset
– Illegal Opcode Detection with Optional Reset
– Illegal Address Detection with Optional Reset
? Low-Power Design (Fully Static with Stop and Wait Modes)
? Master Reset Pin and Power-On Reset
Features of the CPU08 include:
? Enhanced HC05 Programming Model
? Extensive Loop Control Functions
? 16 Addressing Modes (Eight More Than the HC05)
? 16-Bit Index Register and Stack Pointer
? Memory-to-Memory Data Transfers
? Fast 8 × 8 Multiply Instruction
? Fast 16/8 Divide Instruction
? Binary-Coded Decimal (BCD) Instructions
? Optimization for Controller Applications
? C Language Support
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---|---|---|---|---|---|---|---|
FREESCALE/飛思卡爾 |
24+23+ |
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12580 |
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20+ |
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500 |
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3000 |
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22+ |
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3000 |
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詢價(jià) | ||
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QFP |
68900 |
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詢價(jià) | |||
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詢價(jià) | ||
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23+ |
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詢價(jià) | ||
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22+ |
PLCC52 |
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詢價(jià) | ||
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詢價(jià) |