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MC68HC16Z2中文資料飛思卡爾數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

MC68HC16Z2
廠商型號(hào)

MC68HC16Z2

功能描述

M68HC16Z Series

文件大小

5.24019 Mbytes

頁(yè)面數(shù)量

500 頁(yè)

生產(chǎn)廠商 Freescale Semiconductor, Inc
企業(yè)簡(jiǎn)稱

freescale飛思卡爾

中文名稱

飛思卡爾半導(dǎo)體官網(wǎng)

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更新時(shí)間

2025-1-10 10:33:00

MC68HC16Z2規(guī)格書(shū)詳情

INTRODUCTION

M68HC16 Z-series microcontrollers (including the MC68HC16Z1, MC68CM16Z1, MC68CK16Z1, MC68HC16Z2, MC68HC16Z3, MC68HC16Z4, and MC68CK16Z4) are high-speed 16-bit control units that are upwardly code compatible with M68HC11 controllers. All are members of the M68HC16 Family of modular microcontrollers.

M68HC16 microcontroller units (MCUs) are built from standard modules that interface via a common internal bus. Standardization facilitates rapid development of devices tailored for specific applications

OVERVIEW

This section provides general information on M68HC16 Z-series MCUs. It lists features of each of the modules, shows device functional divisions and pin assignments, summarizes signal and pin functions, discusses the intermodule bus, and provides system memory maps. Timing and electrical specifications for the entire microcontroller and for individual modules are provided in APPENDIX A ELECTRICAL CHARACTERISTICS. Comprehensive module register descriptions and memory maps are provided in APPENDIX D REGISTER SUMMARY.

.

M68HC16 Z-Series MCU Features

The following paragraphs highlight capabilities of each of the MCU modules. Each module is discussed separately in a subsequent section of this manual.

Central Processor Unit (CPU16/CPU16L)

? 16-bit architecture

? Full set of 16-bit instructions

? Three 16-bit index registers

? Two 16-bit accumulators

? Control-oriented digital signal processing capability

? Addresses up to 1 Mbyte of program memory; 1 Mbyte of data memory

? Background debug mode

? Fully static operation

? Expanded LPSTOP operation on CPU16L (MC68HC16Z4, MC68CK16Z4 only)

System Integration Module (SIM/SIML)

? External bus support

? Programmable chip-select outputs

? System protection logic

? Watchdog timer, clock monitor, and bus monitor

? Two 8-bit dual function input/output ports

? One 7-bit dual function output port

? Phase-locked loop (PLL) clock system

? Expanded LPSTOP operation on SIML (MC68HC16Z4, MC68CK16Z4 only)

Standby RAM (SRAM)

? 1-Kbyte static RAM (MC68HC16Z1/Z4 only)

? 2-Kbyte static RAM (MC68HC16Z2 only)

? 4-Kbyte static RAM (MC68HC16Z3 only)

? External standby voltage supply input

Masked ROM Module (MRM) — (MC68HC16Z2/Z3 Only)

? 8-Kbyte array, accessible as bytes or words

? User-selectable default base address

? User-selectable bootstrap ROM function

? User-selectable ROM verification code

Analog-to-Digital Converter (ADC)

? Eight channels, eight result registers

? Eight automated modes

? Three result alignment modes

Queued Serial Module (QSM)

? Enhanced serial communication interface

? Queued serial peripheral interface

? One 8-bit dual function port

Multichannel Communication Interface (MCCI) — (MC68HC16Z4/CKZ4 Only)

? Two channels of enhanced SCI (UART)

? One channel of SPI

General-Purpose Timer (GPT)

? Two 16-bit free-running counters with prescaler

? Three input capture channels

? Four output compare channels

? One input capture/output compare channel

? One pulse accumulator/event counter input

? Two pulse width modulation outputs

? Optional external clock input

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