MC68LC040FE25B中文資料飛思卡爾數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

INTRODUCTION

The MC68040, MC68040V, MC68LC040, MC68EC040, and MC68EC040V (collectively called M68040) are Motorola’s third generation of M68000-compatible, high-performance, 32-bit microprocessors. All five devices are virtual memory microprocessors employing multiple concurrent execution units and a highly integrated architecture that provides very high performance in a monolithic HCMOS device. They integrate an MC68030-compatible integer unit (IU) and two independent caches. The MC68040, MC68040V, and MC68LC040 contain dual, independent, demand-paged memory management units (MMUs) for instruction and data stream accesses and independent, 4-Kbyte instruction and data caches. The MC68040 contains an MC68881/MC68882-compatible floatingpoint unit (FPU). The use of multiple independent execution pipelines, multiple internal buses, and a full internal Harvard architecture, including separate physical caches for both instruction and data accesses, achieves a high degree of instruction execution parallelism on all three processors. The on-chip bus snoop logic, which directly supports cache coherency in multimaster applications, enhances cache functionality.

FEATURES

The main features of the M68040 are as follows:

? 6-Stage Pipeline, MC68030-Compatible IU

? MC68881/MC68882-Compatible FPU

? Independent Instruction and Data MMUs

? Simultaneously Accessible, 4-Kbyte Physical Instruction Cache and 4-Kbyte Physical Data Cache

? Low-Latency Bus Accesses for Reduced Cache Miss Penalty

? Multimaster/Multiprocessor Support via Bus Snooping

? Concurrent IU, FPU, MMU, and Bus Controller Operation Maximizes Throughput

? 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface

? User Object-Code Compatible with All Earlier M68000 Microprocessors

? 4-Gbyte Direct Addressing Range

? Software Support Including Optimizing C Compiler and UNIX? System V Port