The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

Features

? Ideal for Addressable Register Applications

? Clock Enable for Address and Data Synchronization Applications

? Eight Edge-Triggered D Flip-Flops

? Buffered Common Clock

? Outputs Source/Sink 24 mA

? See MC74AC273 for Master Reset Version

? See MC74AC373 for Transparent Latch Version

? See MC74AC374 for 3-State Version

? ACT377 Has TTL Compatible Inputs

? MSL = 1 for all Surface Mount

? Chip Complexity: 292 FETs or 73 Gates

? Pb?Free Packages are Available

MC74AC377DW屬于集成電路（IC） > 觸發(fā)器。安森美半導(dǎo)體公司制造生產(chǎn)的MC74AC377DW觸發(fā)器觸發(fā)器是能夠存儲單個邏輯狀態(tài)或信息“位”的基本數(shù)字存儲器件。這些器件至少有兩個輸入；一個或多個用于傳遞要存儲的數(shù)據(jù)，另一個用于指示存儲該數(shù)據(jù)的時間點。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對提供給其輸入的信號有不同的響應(yīng)，可用于實現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時鐘信號時才會改變。