MC74VHCT139ADT集成電路（IC）的信號開關(guān)多路復(fù)用器解碼器規(guī)格書PDF中文資料

MC74VHCT139ADT屬于集成電路（IC）的信號開關(guān)多路復(fù)用器解碼器。由安森美半導(dǎo)體公司制造生產(chǎn)的MC74VHCT139ADT信號開關(guān)，多路復(fù)用器，解碼器邏輯型信號開關(guān)、多路復(fù)用器和編碼器 IC 可用于對以數(shù)字格式表示數(shù)據(jù)的電信號進(jìn)行路由和選擇。這些器件與設(shè)計(jì)用于模擬信號的類似產(chǎn)品有所不同，它們保留的信息表示為兩個(gè)電狀態(tài)之一，而不是兩個(gè)外部界限內(nèi)的無窮變化量。

Dual 2?to?4 Decoder/Demultiplexer

The MC74VHCT139A is an advanced high speed CMOS 2?to?4 decoder/demultiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL devices while maintaining CMOS low power dissipation.

When the device is enabled (E = low), it can be used for gating or as a data input for demultiplexing operations. When the enable input is held high, all four outputs are fixed high, independent of other inputs. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.

The device output is compatible with TTL?type input thresholds and the output has a full 5.0 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic?level translator from 3.0 V CMOS logic to 5.0 V CMOS logic, or from 1.8 V CMOS logic to 3.0 V CMOS logic while operating at the high?voltage power supply

The MC74VHCT139A input structure provides protection when voltages up to 7.0 V are applied, regardless of the supply voltage. This allows the MC74VHCT139A to be used to interface 5.0 V circuits to 3.0 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage?input/output voltage mismatch, battery backup, hot insertion, etc.

Features

? High Speed: tPD = 5.0 ns (Typ) at VCC = 5.0 V

? Low Power Dissipation: ICC = 4 μΑ (Max) at TA = 25°C

? TTL?Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V

? Power Down Protection Provided on Inputs and Outputs

? Balanced Propagation Delays

? Designed for 2.0 V to 5.5 V Operating Range

? Low Noise: VOLP = 0.8 V (Max)

? Pin and Function Compatible with Other Standard Logic Families

? Latchup Performance Exceeds 300 mA

? ESD Performance:

Human Body Model > 2000 V;

Machine Model > 200 V

? Chip Complexity: 100 FETs or 25 Equivalent Gates

? Pb?Free Packages are Available*