MC9S12KT256CPU中文資料恩智浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書

Features

HCS12 Core

–16-bit HCS12 CPU

i. Upward compatible with M68HC11 instruction set

ii. Interrupt stacking and programmer’s model identical to M68HC11

iii. Instruction queue

iv. Enhanced indexed addressing

–MEBI (Multiplexed External Bus Interface)

–MMC (Memory Map and Interface)

–INT (Interrupt Controller)

–DBG (Debugger)

–BDM (Background Debug Mode)

Oscillator

–4Mhz to 16Mhz frequency range

–Pierce with amplitude loop control

–Clock monitor

Clock and Reset Generator (CRG)

–Phase-locked loop clock frequency multiplier

–Self Clock mode in absence of external clock

–COP watchdog

–Real Time interrupt (RTI)

Memory

–32K, 64K, 128K or 256K Byte Flash EEPROM

i. Internal program/erase voltage generation

ii. Security and Block Protect bits

iii. Hamming Error Correction Coding (ECC)

–1K, 2K or 4K Byte EEPROM

–2K, 4K, 6K, 8K or 12K Byte static RAM

Single-cycle misaligned word accesses without wait states

Analog-to-Digital Converter(s) (ADC)

–One 16-channel module with 10-bit resolution except for MC9S12KT256 and MC9S12KG256

–Two 8-channel module with 10-bit resolution for MC9S12KT256 and MC9S12KG256

–External conversion trigger capability

8-channel Timer (TIM)

–Programmable input capture or output compare channels

–Simple PWM mode

–Counter Modulo Reset

–External Event Counting

–Gated Time Accumulation

8-channel Pulse Width Modulator (PWM)

–Programmable period and duty cycle per channel

–8-bit 8-channel or 16-bit 4-channel

–Edge and center aligned PWM signals

–Emergency shutdown input

Two or Three 1M bit per second, CAN 2.0 A, B software compatible modules

–Five receive and three transmit buffers

–Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

–Four separate interrupt channels for Rx, Tx, error and wake-up

–Low-pass filter wake-up function

–Loop-back for self test operation

Serial interfaces

–Two asynchronous serial communication interface (SCI)

–Three synchronous serial peripheral interface (SPI)

–Inter-IC Bus (IIC)

Internal 2.5V Regulator

–Input voltage range from 3.15V to 5.5V

–Low power mode capability

–Low Voltage Reset (LVR) and Low Voltage Interrupt (LVI)

20 key wake up inputs

–Rising or falling edge triggered interrupt capability

–Digital filter to prevent short pulses from triggering interrupts

–Programmable pull ups and pull downs

Operating frequency for ambient temperatures (TA -40°C to 125°C)

–50MHz equivalent to 25MHz Bus Speed

112-Pin LQFP, 100-Pin LQFP, or 80-Pin QFP package

–I/O lines with 3.3V/5V input and drive capability

–3.3V/5V A/D converter inputs