MCM62486B中文資料摩托羅拉數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

32K x 9 Bit BurstRAM Synchronous Static RAM

With Burst Counter and Self–Timed Write

The MCM62486B is a 294,912 bit synchronous static random access memory designed to provide a burstable, high–performance, secondary cache for the i486 and Pentium? microprocessors. It is organized as 32,768 words of 9 bits, fabricated with Motorola’s high–performance silicon–gate CMOS technology. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

The MCM62486B will be available in a 44–pin plastic leaded chip carrier (PLCC). Multiple power and ground pins have been utilized to minimize effects induced by output noise. Separate power and ground pins have been employed for DQ0 – DQ8 to allow user–controlled output levels of 5 volts or 3.3 volts.

? Single 5 V ± 10 Power Supply (± 5 for MCM62486BFN11)

? Choice of 5 V or 3.3 V ± 10 Power Supplies for Output Level Compatibility

? Fast Access Times:11/12/14/19 ns Max and Cycle Times:15/20/25 ns Min

? Internal Input Registers (Address, Data, Control)

? Internally Self–Timed Write Cycle

? ADSP, ADSC, and ADV Burst Control Pins

? Asynchronous Output Enable Controlled Three–State Outputs

? Common Data Inputs and Data Outputs

? High Output Drive Capability: 85 pF per I/O

? High Board Density PLCC Package

? Fully TTL–Compatible

? Active High and Low Chip Select Inputs for Easy Depth Expansion