MCM63P636TQ200R中文資料摩托羅拉數(shù)據(jù)手冊PDF規(guī)格書

64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

The MCM63P636 is a 2M–bit synchronous fast static RAM designed to provide burstable, high performance, secondary cache for advanced microprocessors. It is organized as 64K words of 36 bits each. This device integrates input registers, an output register, a 2–bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows for precise cycle control with the use of an external clock (K) and external strobe clock (SK).

The MCM63P636 operates from a 3.3 V core power supply, a 2.0 V input power supply, and a 2.0 V I/O power supply. These power supplies are designed so that power sequencing is not required.

? MCM63P636–250 = 3.9 ns Access/4 ns Cycle (250 MHz)

MCM63P636–225 = 4.3 ns Access/4.4 ns Cycle (225 MHz)

MCM63P636–200 = 4.9 ns Access/5 ns Cycle (200 MHz)

? 3.3 V ± 200 mV VDD Supply, 2.0 V VDDI and VDDQ Supply

? Internally Self–Timed Late Write Cycle

? Three–Cycle Single–Read Latency

? Strobe Clock Input and Data Strobe Output Pins

? On–Chip Output Enable Control

? On–Chip Burst Advance Control

? Four–Tick Burst

? Power–On Reset Pin

? Low Power Stop Clock Operation

? Boundary Scan (PBGA Only)

? JEDEC Standard 153–Pin PBGA and 100–Pin TQFP Packages