MCM69P618CTQ4.5中文資料摩托羅拉數(shù)據(jù)手冊PDF規(guī)格書

64K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

The MCM69P618C is a 1M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC?, 486, i960?, and Pentium? microprocessors. It is organized as 64K words of 18 bits each. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

The MCM69P618C operates from a single 3.3 V power supply and all inputs and outputs are LVTTL compatible and 5 V tolerant.

? MCM69P618C–4 = 4 ns Access / 7.5 ns Cycle

MCM69P618C–4.5 = 4.5 ns Access / 8 ns Cycle

MCM69P618C–5 = 5 ns Access / 10 ns Cycle

MCM69P618C–6 = 6 ns Access / 12 ns Cycle

MCM69P618C–7 = 7 ns Access / 13.3 ns Cycle

? Single 3.3 V + 10, – 5 Power Supply

? ADSP, ADSC, and ADV Burst Control Pins

? Selectable Burst Sequencing Order (Linear/Interleaved)

? Internally Self–Timed Write Cycle

? Byte Write and Global Write Control

? Single–Cycle Deselect Timing

? 5 V Tolerant on all Pins (Inputs and I/Os)

? 100–Pin TQFP Package