MCM72BF64SG66中文資料摩托羅拉數(shù)據(jù)手冊PDF規(guī)格書

256KB and 512KB BurstRAM? Secondary Cache Module for Pentium?

The MCM72BF32SG and MCM72BF64SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor. The modules are configured as 32K x 72 and 64K x 72 bits in a 160 pin card edge memory module. Each module uses four of Motorola’s MCM67B518 or MCM67B618 BiCMOS BurstRAMs. All 72 I/Os are series terminated for added noise immunity.

Bursts can be initiated with either address status processor (ADSP) or address status controller (ADSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst advance (ADV) input pin.

Write cycles are internally self timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control.

The cache family is designed to interface with popular Pentium cache controllers with on board tag.

PD0 – PD2 are reserved for density identification.

? Pentium–style Burst Counter on Chip

? Flow–Through Data

? 160 Pin Card Edge Module

? Single 5 V ± 5 Power Supply

? All Inputs and Outputs are TTL Compatible

? Three State Outputs

? Byte Parity, Byte Write Enables

? Fast Module Clock Rates: 66 MHz, 60 MHz

? Decoupling Capacitors for each Fast Static RAM

? High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes

? I/Os are 3.3 V Compatible

? Burndy Connector, Part Number: CELP2X80SC3Z48

? Series 20 ? Resistors for Noise Immunity