MCM72F8中文資料摩托羅拉數(shù)據(jù)手冊PDF規(guī)格書

The MCM72F8 (2MB) is configured as 256K x 72 bits and the MCM72F9 (4MB) is configured as 512K x 72 bits. Both are packaged in a 168–pin dual–in–line memory module DIMM. Each module uses Motorola’s 3.3 V 256K x 18 bit flow–through BurstRAMs.

Address (A), data inputs (DQ, DP), and all control signals except output enable (G) are clock (K) controlled through positive–edge–triggered noninverting registers.

Write cycles are internally self–timed and initiated by the rising edge of the clock (K) input. This feature provides increased timing flexibility for incoming signals. Synchronous byte write (W) allows writes to either individual bytes or to both bytes.

? Single 3.3 V + 10, – 5 Power Supply

? Plug and Pin Compatibility with 2MB and 4MB

? Multiple Clock Pins for Reduced Loading

? All Inputs and Outputs are LVTTL Compatible

? Byte Write Capability

? Fast SRAM Access Times: 8/9/12 ns

? Decoupling Capacitors for Each Fast Static RAM

? High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes

? Amp Connector, Part Number: 390064–4

? 168–Pin DIMM Module