MCXN235VDFT中文資料恩智浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書

Features[1]

? Arm Cortex-M33 150MHz with 618 CoreMark? (4.12 CoreMark/MHz)

? Up to 1MB Flash, 352 KB SRAM

? Platform Security with EdgeLock? Secure Enclave, Core Profile

? - 40 °C to + 125 °C temperature range

? Down to 50 μA/MHz active current, 3.0 μA Power down mode with RTC

enabled and 352 KB SRAM retention, 1.5 μA Deep Power-down mode

with RTC active and 32 KB SRAM

Cores

? Arm 32-bit Cortex-M33 CPU with TrustZone?, MPU, FPU, SIMD, ETM and CTI

Processing Accelerators

? SmartDMA (co-processor for applications such as parallel camera interface and keypad scanning)

Memories

? Up to 1 MB (2 x 512KB Bank) on chip Flash memory supporting Flash Swap and Read While Write, with ECC (support

one bit correction and two bits detection)

? Cache Engine with 16 KB RAM

? Up to 352 KB RAM, configurable as up to 288 KB with ECC (support one bit correction and two bits detection)

? Up to 4x 8 KB ECC RAM can be retained down to VBAT mode

? 256 KB ROM with secure bootloader

Security

? EdgeLock Secure Enclave,Core Profile

— Cryptographic services (incl. AES-256, SHA-2, ECC NIST P-256, TRNG and key generation/derivation)

— Secure key store with key usage policies (protection of platform integrity, manufacturing and applications keys)

— Device Unique Identity based on Physically Unclonable Function (PUF)

— Device Attestation with support of Device Identifier Composition Engine (DICE)

— Secure connection and TLS support

— Key management over-the-air with pre-integration of NXP EdgeLock 2GO

? EdgeLock Accelerator (Public Key Cryptography)

? Immutable secure boot code in ROM

? Dual Secure Boot Mode (asymmetric mode and fast, post-quantum secure symmetric mode)

? Secure firmware update support