MH28S72PJG-7中文資料三菱電機數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The MH28S72PJG is 134,217,728 - word x 72-bit Sy nchronous DRAM stacked structural module. This consist of thirty -six industry standard 64M x 4 Sy nchronous DRAMs in TSOP.

The stacked structure of TSOP on a card edge dual inline package prov ides any application where high densities and large of quantities memory are required.

This is a socket-ty pe memory module ,suitable f or easy interchange or addition of module.

FEATURES

? Utilizes industry standard 64M X 4 Synchronous DRAMs in TSOP package , industry standard Resister in TSSOP package , and industrystandard PLL in TSSOP package.

? Single 3.3V +/- 0.3V supply

? Burst length 1/2/4/8/Full Page (programmable)

? Burst type sequential / interleave (programmable)

? Column access random

? Burst W rite / Single W rite (programmable)

? Auto precharge / Auto bank precharge controlled by A10

? Auto refresh and Self refresh

? LVTTL Interface

? 8192 refresh cycles every 64ms

APPLICATION

Main memoryunit for computers, Microcomputer memory.