MH32D72AKLA-75中文資料三菱電機(jī)數(shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION

The MH32D72AKLA is 33554432 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.

This consists of 18 industry standard 32M x 4 DDR Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which achiev es v ery high speed data rate up to 133MHz.

This socket-ty pe memory module is suitable f or main memory in computer systems and easy to interchange or add modules.

FEATURES

- Utilizes industry standard 32M X 4 DDR Synchronous DRAMs in TSOP package , industry standard Registered Buffer in TSSOP package , and industry standard PLL in TSSOP package.

- Vdd=Vddq=2.5v ±0.2V

- Double data rate architecture; two data transf ers per clock cycle

- Bidirectional, data strobe (DQS) is transmitted/receiv ed with data

- Dif f erential clock inputs (CLK and /CLK)

- data ref erenced to both edges of DQS

- /CAS latency - 2.0/2.5 (programmable)

- Burst length- 2/4/8 (programmable)

- Auto precharge / All bank precharge controlled by A10

- 4096 ref resh cycles /64ms

- Auto ref resh and Self ref resh

- Row address A0-11 / Column address A0-9,11

- SSTL_2 Interf ace

- Module 1bank Conf igration

- Burst Ty pe - sequential/interleav e(programmable)

- Commands entered on each positiv e CLK edge

APPLICATION

Main memoryunit for PC, PC server