首頁(yè)>MH64S64APFH-7>規(guī)格書(shū)詳情
MH64S64APFH-7中文資料三菱電機(jī)數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
廠商型號(hào) |
MH64S64APFH-7 |
功能描述 | 4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM |
文件大小 |
604 Kbytes |
頁(yè)面數(shù)量 |
52 頁(yè) |
生產(chǎn)廠商 | Mitsubishi Electric Semiconductor |
企業(yè)簡(jiǎn)稱 |
Mitsubishi【三菱電機(jī)】 |
中文名稱 | 三菱電機(jī)半導(dǎo)體(Mitsubishi Electric Semiconductor)官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2024-11-8 9:30:00 |
MH64S64APFH-7規(guī)格書(shū)詳情
DESCRIPTION
The MH64S64APFH is 67108864 - word by 64-bit Synchronous DRAM module. This consists of sixteen industry standard 32Mx8 Synchronous DRAMs in Small TSOP and one industory standard EEPROM in TSSOP.
The mounting of Small TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required.
This is a socket type - memory modules, suitable for easy interchange or addition of modules.
FEATURES
? Utilizes industry standard 32M x 8 Synchronous DRAMs Small TSOP and industry standard EEPROM in TSSOP
? 144-pin (72-pin dual in-line package)
? single 3.3V±0.3V power supply
? Max. Clock frequency -6:133MHz,-7:100MHz
? Fully synchronous operation referenced to clock rising edge
? 4 bank operation controlled by BA0,1(Bank Address)
? /CAS latency- 2/3(programmable)
? Burst length- 1/2/4/8/Full Page(programmable)
? Burst type- sequential / interleave(programmable)
? Column access - random
? Auto precharge / All bank precharge controlled by A10
? Auto refresh and Self refresh
? 8192 refresh cycle /64ms
? LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
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DENSO/ND |
CCD20 |
6500 |
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3000 |
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8560 |
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2000 |
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詢價(jià) | ||
MOT |
23+ |
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4500 |
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13 |
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MITSUBISHI |
23+ |
NA |
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詢價(jià) | ||
MOTOROLA/摩托羅拉 |
22+ |
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9600 |
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2016+ |
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6528 |
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詢價(jià) | ||
MOTOROLA/摩托羅拉 |
22+ |
PLCC |
6550 |
原裝 低價(jià) 支持實(shí)單 |
詢價(jià) |