MH8D64AKQC-75中文資料三菱電機數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The MH8D64AKQC is 8388608 - word x 64-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.

This consists of 4 industry standard 8M x 16 DDR Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which achiev es v ery high speed data rate up to 133MHz.

This socket-ty pe memory module is suitable f or main memory in computer systems and easy to interchange or add modules.

FEATURES

- Utilizes industry standard 8M X 16 DDR Synchronous DRAMs in TSOP package , industry standard EEPROM(SPD) in TSSOP package

- 200pin SO-DIMM

- Vdd=Vddq=2.5v ±0.2V

- Double data rate architecture; two data transf ers per clock cycle

- Bidirectional, data strobe (DQS) is transmitted/receiv ed with data

- Dif f erential clock inputs (CLK and /CLK)

- DLL aligns DQ and DQS transitions with CLK transition edges of DQS

- Commands entered on each positiv e CLK edge

- Data and data mask ref erenced to both edges of DQS

- 4bank operation concontrolled by BA0,BA1(Bank Address ,discrete)

- /CAS latency - 2.0/2.5 (programmable)

- Burst length- 2/4/8 (programmable)

- Burst Ty pe - sequential/interleav e(programmable)

- Auto precharge / All bank precharge controlled by A10

- 4096 ref resh cycles /64ms

- Auto ref resh and Self ref resh

- Row address A0-11 / Column address A0-8

- SSTL_2 Interf ace

- Module 1bank Conf igration

APPLICATION

Main memoryunit for Note PC, Mobile etc.