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MH8S72BMG-10中文資料三菱電機(jī)數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

MH8S72BMG-10
廠商型號(hào)

MH8S72BMG-10

功能描述

603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM

文件大小

589.75 Kbytes

頁(yè)面數(shù)量

55 頁(yè)

生產(chǎn)廠商 Mitsubishi Electric Semiconductor
企業(yè)簡(jiǎn)稱

Mitsubishi三菱電機(jī)

中文名稱

三菱電機(jī)株式會(huì)社官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-8 11:13:00

MH8S72BMG-10規(guī)格書(shū)詳情

DESCRIPTION

The MH8S72BMG is 8388608 - word by 72-bit Synchronous DRAM module. This consists of ten industry standard 4Mx16 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP.

The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required.

This is a socket type - memory modules, suitable for easy interchange or addition of modules.

FEATURES

? Utilizes industry standard 4M x 16 Synchronous DRAMs TSOP and industry standard EEPROM in TSSOP

? 168-pin (84-pin dual in-line package)

? single 3.3V±0.3V power supply

? Clock frequency 100MHz

? Fully synchronous operation referenced to clock rising edge

? 4 bank operation controlled by BA0,1(Bank Address)

? /CAS latency- 2/3(programmable)

? Burst length- 1/2/4/8/Full Page(programmable)

? Burst type- sequential / interleave(programmable)

? Column access - random

? Auto precharge / All bank precharge controlled by A10

? Auto refresh and Self refresh

? 4096 refresh cycle /64ms

? LVTTL Interface

? Discrete IC and module design conform to PC100 specification.

(module Spec. Rev. 1.0 and SPD 1.2A(-7,-8), SPD 1.0(-10))

APPLICATION

PC main memory

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