MIMXRT102LXVJ4A中文資料恩智浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書

Features

The i.MX RT1015 processors are based on Arm Cortex-M7 Core? Platform, which has the following

features:

? Supports single Arm Cortex-M7 with:

— 16 KB L1 Instruction Cache

— 16 KB L1 Data Cache

— Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture

— Support the Armv7-M Thumb instruction set

? Integrated MPU, up to 16 individual protection regions

? Up to 128 KB I-TCM and D-TCM in total

? Frequency of 500 MHz

? Cortex M7 CoreSight? components integration for debug

? Frequency of the core, as per Table 9, Operating ranges, on page 17.

The SoC-level memory system consists of the following additional components:

— Boot ROM (96 KB)

— On-chip RAM (128 KB)

– Configurable RAM size up to 128 KB shared with CM7 TCM

? External memory interfaces:

— SPI NOR/NAND FLASH

— Parallel NOR FLASH with XIP support

— Single/Dual channel Quad SPI FLASH with XIP support

? Timers and PWMs:

— Two General Programmable Timers

– 4-channel generic 32-bit resolution timer

– Each support standard capture and compare operation

— Four Periodical Interrupt Timers

– Generic 32-bit resolution timer

– Periodical interrupt generation

— One Quad Timer

– 4-channel generic 16-bit resolution timer

– Each support standard capture and compare operation

– Quadrature decoder integrated

— One FlexPWM

– Up to 8 individual PWM channels

– 16-bit resolution PWM suitable for Motor Control applications

— One Quadrature Encoder/Decoder

Each i.MX RT1015 processor enables the following interfaces to external devices (some of them are

multiplexed and not available simultaneously):

? Audio:

— S/PDIF input and output

— Three synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and

codec/DSP interfaces

— MQS interface for medium quality audio via GPIO pads

? Connectivity:

— One USB 2.0 OTG controller with integrated PHY interface

— Four universal asynchronous receiver/transmitter (UARTs) modules

— Two I2C modules

— Two SPI modules

? GPIO and Pin Multiplexing:

— General-purpose input/output (GPIO) modules with interrupt capability

— Input/output multiplexing controller (IOMUXC) to provide centralized pad control

— 57 GPIOs

— One FlexIO

The i.MX RT1015 processors integrate advanced power management unit and controllers:

? Full PMIC integration, including on-chip DCDC and LDOs

? Temperature sensor with programmable trip points

? GPC hardware power management controller

The i.MX RT1015 processors support the following system debug:

? Arm CortexM7 CoreSight debug and trace architecture

? Trace Port Interface Unit (TPIU) to support off-chip real-time trace

? Support for 5-pin (JTAG) and SWD debug interfaces selected by eFuse

Security functions are enabled and accelerated by the following hardware:

? High Assurance Boot (HAB)

? Data Co-Processor (DCP):

— AES-128, ECB, and CBC mode

— SHA-1 and SHA-256

— CRC-32

? Bus Encryption Engine (BEE)

— AES-128, ECB, and CTR mode

— On-the-fly QSPI Flash decryption

? True random number generation (TRNG)

? Secure Non-Volatile Storage (SNVS)

— Secure real-time clock (RTC)

— Zero Master Key (ZMK)

? Secure JTAG Controller (SJC)