MK2058-01集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器規(guī)格書(shū)PDF中文資料

Features

? Excellent jitter attenuation for telecom clocks

? Also serves as a general purpose clock jitter attenuator

for distributed system clocks and recovered data or video

clocks

? 2:1 Input MUX for input reference clocks

? No switching glitches on output

? VCXO-based clock generation offers very low jitter and

phase noise generation

? Output clock is phase and frequency locked to the

selected input reference clock

? Fixed input to output phase relationship

? +115ppm minimum crystal frequency pullability range,

using recommended crystal

? Industrial temperature range

? Low power CMOS technology

? 20-pin SOIC package

? Pb (lead) free package

? Single 3.3 V power supply